Intel brings Many Integrated Core plans to HPC

Intel announced a new Many Integrated Core (MIC) architecture at the International Supercomputing Conference in Hamburg today.

Targeting high-performance computing segments, the first product, codenamed Knights Corner, will be built on Intel's 22-nanometre process, with, Intel said, more than 50 processing cores on a single chip.

Intel said MIC architecture is derived from several Intel projects, including dead/undead Larrabee and such Intel Labs research projects as the Single-chip Cloud Computer.

Kirk Skaugen, vice president and general manager of Intel's data centre group showed off the technology on stage in Hamburg, saying the architecture enables a large core count and high memory usage, with a mixture of large and small cores, with co-processors added using the PCIe bus. The first PCIe implementation features 32 cores with four threads per core and 4MB of shared cache, in the standard PCIe thermal envelope, Skaugen said.

He said the Xeon 7500 architecture had been tweaked with 100 new instructions for the architecture.

Industry design and development kits, codenamed Knights Ferry, are currently shipping to select developers, and Intel said that it will expand the programme to deliver an extensive range of developer tools for Intel MIC architecture beginning in the second half of 2010.

The MIC architecture will help accelerate select highly-parallel applications with common Intel software tools and optimisation techniques between Intel MIC architecture and Intel Xeon processors to support diverse programming models, allowing HPC users to preserve their existing software investments.

In a statement, Sverre Jarp, CTO of CERN openlab said the CERN openlab team, "was able to migrate a complex C++ parallel benchmark to the Intel MIC software development platform in just a few days.

"The familiar hardware programming model allowed us to get the software running much faster than expected," he said.

Intel said there were more long Knights to come.