AMD offers up new Bulldozer details at ISSCC

AMD has revealed some more in-depth details about its upcoming Bulldozer processor architecture in a series of papers for the International Solid State Circuits Conference.

Bulldozer, which is AMD's most innovative redesign for its core processor line in quite some years, promises to bring massive improvements in multi-processor scaling to servers and desktops but, despite a series of technical documents from the company, relatively little is known about the ins and outs of the new architecture.

The chip maker has decided to release some more details at the ISSCC this week in the form of two technical presentations: 'Design solutions for the Bulldozer 32n SOI 2-core processor module in an 8-core CPU,' and '40-entry unified, out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core.'

The first session builds on the details released by the company at last year's HotChips conference, offering an insight into the design of the floating point unit built into the Bulldozer CPU. Detailed in the presentation are enhancements including totally redesigned arithmetic units, control structures, and power improvements designed to increase efficiency while decreasing power draw. Also included are the previously-known additional instructions present in Bulldozer, including SSE3, SSE4.1, SSE4.2, AVX, AES, and advanced Multiply-Add/Accumulate operations.

The presentation also describes the work carried out by AMD to ensure maximum performance from the 32nm silicon-on-insulator fabrication process used to build the chips by fab spin-off GlobalFoundries. Included are details about improved power management techniques, on-chip memories, and a new low-power flop design - similar to that announced recently by Toshiba, and designed to further reduce power draw and heat output.

The second presentation covers changes to the processor's integer execution unit, which has been completely overhauled from previous generations in order to improve performance while reducing power draw - and introducing the ability to handle up to four 64-bit instructions per thread.

AMD's Bulldozer architecture is designed to share resources including the floating point unit between a pair of processing cores, reducing the component count while enabling something the company calls chip-multithreading - which it claims offers drastic improvements over the HyperThreading technology from rival Intel.

Bulldozer is also expected to bring significant improvements in scalability, allowing multiple dual-core Bulldozer modules to be integrated into a single many-core package without the drop in performance traditionally associated with such designs.

Sadly, the full text of both presentations has yet to be made public.