Veteran of microcomputing Steve Furber, in his role as ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester, has called upon some old friends for his latest project: a brain-simulating supercomputer based on more than a million ARM processors.
Those who missed the home computing revolution of the eighties might not be familiar with Furber's work, but his impact is not to be underestimated: while working at Acorn - founded by Chris Curry, Hermann Hauser, and Andy Hopper after the former left Clive Sinclair's company following a fundamental disagreement - Furber worked with engineer Sophie Wilson on developing the ARM architecture, a chip based on which is almost certainly inside your smartphone as you read this.
While Furber left the ailing Acorn in 1990, as the microcomputing boom hit a sudden slump, he has worked in the field of computing ever since. Unlike such creations as the Acorn Electron and the RiscPC, however, Furber's latest project is a bit more ambitious: an electronic brain.
The project's name is SpiNNaker - Spiking Neural Network architecture - and it aims at nothing less than using a biologically-inspired massively parallel computing system to simulate spiking neurons in biological real time. It's a task which requires high-speed communication between the system's components, meaning that traditional cluster computing models are simply not up to the task.
To overcome this limitation, Furber - along with Andrew Brown, from the University of Southampton - suggests an innovative system architecture that takes its cues from nature. "The approach taken towards this goal is to develop a massively-parallel computer architecture based on Multi-Processor System-on-Chip technology capable of modelling a billion spiking neurons in biological real time, with biologically realistic levels of connectivity between the neurons," Furber explains in a white paper outlining the project.
It's an architecture which looks more like a cyclotron than a traditional computer mesh, and one which has seen Furber go back to the ARM architecture for components. A two-dimensional toroidal mesh of system-on-chip multiprocessors - with triangular facets, the white paper points out, to support 'emergency routing' around a failed or congested link - the SpiNNaker system as envisioned will be made up of nodes holding up to 20 ARM968 processors and 1GB of LPDDR memory.
While a twenty-core system might not sound like much, Furber's plan is to build SpiNNaker from a large quantity of these nodes: more than 50,000 in total. That would give the team a computing system with more than one million central processing units, requiring a radical rethink of the how inter-processor communication and parallel programming models should operate.
Furber has reasons other than nostalgia for choosing ARM chips for his creation. "Embedded and high-end processors are roughly equal," Furber explains in the white paper. "A SpiNNaker chip with 20 ARM cores delivers about the same throughput as a high-end desktop processor – but on energy efficiency the embedded processors win by an order of magnitude [original emphasis]."
That's one of the key parts of Furber's vision for SpiNNaker: "Processors are free," the document claims. "The real cost of computing is in energy. This has not been true historically," Furber admits, "but the cost of processors is falling and the cost of energy is rising. If this trend continues, as seems likely, then this assertion will become true at some point."
In many ways, the SpiNNaker project echoes Intel's many-core computing vision: an attempt to cram massive amounts of processing power into as small an energy footprint as possible. In Intel's case, it's looking towards general purpose supercomputing and reducing the cost of running a HPC cluster; in Furber's case, the task is rather more specialised but no less important.
"The SpiNNaker project," Furber concludes, "aims to deliver cost-effective parallel computing resources at an unprecedented scale, with over a million embedded processors delivery around 200 teraIPS to support the simulation of a billion spiking neurons in biological real time. The scale of the system demands that power-efficiency and fault-tolerance feature prominently among the design criteria, and the result is a design that embodies concurrency at all levels, from circuit through system to application."
It's a laudable goal, and one that - if successful - could spell a major breakthrough for ARM's chances in the high-performance computing market so beloved of Intel.
Furber and Brown's paper on SpiNNaker can be downloaded as a PDF.
Some people have reported problems downloading the paper, so here's a copy hosted on Scribd.