Intel digs deep for SRAM radiation tests

Intel has been testing some of its chips in a rather novel environment, 2,150 feet below the surface of the Chihuahuan Desert in New Mexico, in order to get to the bottom of errors caused by radiation.

The tiny scale on which modern semiconductors operate make them extremely sensitive to interference, and most chips include a raft of error detection and correction algorithms designed to figure out when an answer isn't quite right and prevent it from making the system fall down hard.

Intel's chips are no different, but the company decided it wasn't happy simply detecting the errors and correcting them but wanted instead to understand what causes them.

That the errors Intel was detecting were caused by tiny amounts of ionizing radiation were well known, but the company was curious as to the source: were the errors caused by the alpha particles being emitted by the material of the chip itself, or from neutrons bombarding the Earth from space?

To find out, a pair of researchers - Norbert Seifert and Matthew Kirsch - went to one of the only places on the planet where cosmic radiation isn't a problem: in a pit, separating the chips from the sky with 2,150 feet of solid rock.

The pit is an old salt mine, borrowed from the US Department of Energy ahead of plans to dump uranium waste where it won't do any harm for a few thousand years. The half-mile rock ceiling means that radiation doesn't get in or out, and allowed the pair to discount the effects of cosmic radiation in their tests.

Using a battery of 45nm SRAM devices running for a year, the researchers were able to determine that around 90 per cent of the 'radiation' errors encountered by the chips came from outside sources while only 10 per cent was a result of the alpha particles emitted from the chip and its packaging.

So far, Intel hasn't explained what it plans to do with the results of the test, but the liklihood is that the company will create a new range of mission-critical devices based on heavily shielded electronics to reduce the already minuscule error rate to previously unheard-of levels.

Such chips will be expensive, of course, but will likely find ready buyers in military and supercomputing applications where requirements for speed and accuracy combine to make cost a tertiary concern.