Deposing silicon: A peek inside IBM’s carbon nanotube computer chip laboratory

At IBM’s Watson Research Centre in upstate New York, some of the world’s best physicists, chemists, and nano-engineers are trying to create the first high density, self-assembling carbon nanotube computer chip process. In much the same way that Jack Kilby at Texas Instruments discovered the monolithic VLSI process for making silicon chips in 1958, IBM desperately wants to find the process that enables the creation of carbon nanotube chips.

In the next decade – or thereabouts, the goalposts keep shifting – silicon is expected to reach a miniaturisation roadblock. At some point, we simply won’t be able to make silicon transistors any smaller. When this happens, there will be a few materials jostling to fill the void, most notably silicon-germanium, galium arsenide, and various forms of carbon (nanotubes, nanowires, graphene).

In theory, computer chips made from carbon nanotubes are massively desirable – they would be many times faster than silicon, use less power, and can scale down to just a couple of nanometres. In practice, working with carbon nanotubes – just like graphene – is proving to be rather difficult. It’s sometimes easy to forget that we have decades of experience and billions worth of R&D ploughed into silicon; expertise with new materials won’t come easy.

Progress is being made, however. Case in point: IBM has now managed to create a 10,000 carbon nanotube transistor chip, on top of a standard silicon wafer (pictured at the top of this article). This is significant for two reasons. Firstly, the process used is very similar to existing silicon chip fabrication processes – and when you’re talking about a trillion-pound industry with stupendous amounts of capital investment in silicon tech, this is a very good thing. Secondly, IBM is reporting that its density of individually positioned carbon nanotubes is two orders of magnitude higher than any other research group’s efforts.

There’s still a lot of work to be done, though. The nanotube transistors are currently spaced 150nm apart, which is much farther than in silicon chips and will need to be reduced to reach the required feature density.

The other problem is that the entire chip of 10,000 transistors currently has only one gate – the silicon wafer itself. Every transistor turns on and off at the same time. To fix this, the IBMers need to add electrodes to each of the carbon nanotubes – a step that also hinders graphene-based transistors. This is one of the key steps that IBM, and probably Intel and other silicon juggernauts, are currently working on.

Below are a few more pictures of IBM’s carbon nanotube computer chip, and the process behind its manufacture…

The above image depicts carbon nanotubes which are produced by burning carbon with an electric arc. About one quarter of the soot is nanotubes.

After the wafer is etched with trenches, it receives two liquid baths to deposit the carbon nanotubes.

An IBMer, sliding the carbon nanotube transistor wafer into a testing machine.

Black electrical probes, testing the carbon nanotube transistors (not visible).

Research paper: http://www.nature.com/nnano/journal/v7/n12/full/nnano.2012.189.html – “High-density integration of carbon nanotubes via chemical self-assembly.”

Image Credit: Andrew Sullivan

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