New materials and transistors: Applied Materials details the road beyond 14nm

At Semicon West 2013, the annual mecca for chipmakers and their capital equipment manufacturers, Applied Materials detailed the road beyond 14nm, all the way down to 3nm and possibly beyond.

The talk, delivered by Adam Brand of Applied Materials, mostly focused on the material and architectural challenges of mass-producing transistors at 14nm and beyond.

At this point, 14nm seems to be the final node where silicon – even when in the shape of a fin (as in FinFETs) – will be thick enough to prevent quantum tunnelling and gate leakage.

(The image below shows transistor gate length, Lg, over time. The plateau was between 45nm and 28nm, until Intel’s 22nm FinFET kicked in).

Beyond 14nm, as we move to 10 and 7nm, a new fin material will be required – probably silicon-germanium (SiGe), or perhaps just pure germanium. SiGe and Ge have higher electron mobility than Si, allowing for lower voltages, and thus reducing power consumption, tunnelling, and leakage. SiGe has been used in commercial CMOS fabrication since the late 80s, too, so switching from silicon won’t be too painful. (The primary reason that we’ve been using silicon for so long is that the entire industry is based on silicon. The amount of time, money, and R&D that would be required to deploy new machines for handling new materials that we know relatively little about would be astronomical.)

According to Brand, SiGe will take us to 7nm – but after that, we’re probably looking at a new transistor structure. Just as FinFET created a larger surface area, mitigating the effects of quantum tunnelling, both Gate All Around (GAA) FETs and vertical tunnelling FETs (TFETs), would again allow for shorter gates and lower voltages.

As you can see in the diagram below, a GAA FET essentially consists of nanowire source and drains, surrounded by a gate. A vertical TFET is similar in that it uses nanowires, but the actual method of operation is very different from conventional FETs.

Again, though, TFETs allow for lower operating voltage. Another option is a somewhat conventional FinFET, but with the fin constructed out of III-V semiconductors such as gallium-arsenide (GaAs), which again have higher electron mobility than silicon.

The path beyond 14nm is treacherous, and by no means a sure thing, but with roadmaps from Intel and Applied Materials both hinting that 5nm is being researched, we remain hopeful. Perhaps the better question to ask, though, is whether it’s worth scaling to such tiny geometries. With each step down, the process becomes ever more complex, and thus more expensive and more likely to be plagued by low yields. There may be better gains to be had from moving sideways, to materials and architectures that can operate at faster frequencies and with more parallelism, rather than brute-forcing the continuation of Moore’s law.

For the complete set of slides, hit up the Semicon West 2013 website [PDF]. Unless you’re a PhD-wielding process chemist working at Intel or TSMC, though, the contents may go over your head.