An in-depth look at the death of Moore’s law

There have been a number of events over the past few weeks that collectively point to serious problems ahead for the semiconductor market and all the players in that space. While some companies will feel the impact more than others, the news isn’t great for anyone. The entire economic structure that was supposed to support both Intel and the major foundries as they moved to next-generation manufacturing technologies, such as 450mm wafers, extreme ultraviolet lithography, and 20nm CMOS, is on the verge of coming apart.

450mm wafers and EUV

18 months ago, TSMC, Intel, and Samsung made headlines when they all poured money into ASML’s efforts to develop 450mm wafers. These were major announcements at the time and they signalled that all of the major logic manufacturers were on the same page when it came to 450mm wafer development.

Then, in December, came news that ASML had hit “pause” on this project. Intel’s 450mm installation at Fab D1X is reportedly on hold, as is the company’s Fab 42 in Arizona.

The CEO of Applied Materials, Gary Dickerson, has stated that the 450mm wafer timeline “has definitely been pushed out from a timing standpoint.” That’s incredibly important, because the economics of 450mm wafers were tied directly to the economics of another struggling technology – EUV (extreme ultraviolet lithography).

EUV is the follow-up to 193nm lithography that’s used for etching wafers, but it’s a technology that’s spent over a decade mired in technological problems and major ramp-up concerns.

One of the single greatest problems is source power. To put this simply – no one, including ASML, has yet demonstrated an EUV tool capable of reaching anything like the necessary power concentrations or of sustaining production volumes. Instead, we’re stuck at the red dot shown above. The enormous costs of shifting to EUV and 450mm wafers were meant to be partly offset by making the jump at the same time.

That might not make sense at first, but remember – EUV was expected to reduce lithography costs (see the image below) by allowing manufacturers to move away from expensive double patterning. The high cost of 450mm wafers and equipment would be offset by superior economies of scale from the larger wafer sizes. Larger wafers also give companies more room to tolerate defect densities (an equal number of defects on a 450mm wafer versus a 300mm wafer means you still get more “good” chips off the larger wafer in absolute terms).

But if EUV doesn’t debut as a 450mm-only feature, then one of the major reasons to update goes down the tubes – and the more time goes by, the harder it gets for EUV to catch up. Without good EUV delivery, 450mm wafers may never make much sense. Samsung is reportedly balking on taking delivery – it’s not willing to risk losing market share to other memory manufacturers if a 450mm installation drive means less 300mm production.

The death of Moore’s law

At the SPIE Advanced Lithography conference at the end of February, a group of lithography engineers – men and women who have spent their careers pushing the boundaries of Moore’s law – toasted its death. This is the economic reality we predicted back in 2012 – flat scaling at 20nm compared to 28nm, and only marginal improvements predicted thereafter.

The video is meant to be funny, but the point isn’t being argued any more. Moore’s law is no longer expected to deliver improved transistor cost scaling at or below the 20nm node. It’s important to understand how that plays into concerns about EUV and 450mm wafers put together. For decades, it’s been a given that GPU and CPU transistor counts would increase every generation and that this would be economical because increased density allowed for a cheaper cost per square millimetre and more chips per die. If cost per square millimetre holds flat but transistor density rises, that means the cost per transistor has increased – and suddenly, those higher transistor counts aren’t nearly so desirable.

This is where 450mm wafers and EUV were supposed to come in. EUV relieves the need for double patterning and the tremendous additional costs that entails. 450mm wafers offer manufacturers far more area to work with, increasing fab productivity and boosting economics by allowing for much greater efficiencies of production. Improve these factors, and the higher per-transistor costs can be carried for a few more generations.

Instead, TSMC was sharply critical of ASML’s progress on EUV at the SPIE conference, and plans for 450mm wafers may have been delayed another nine years. In this industry, a 2023 roadmap for deployment is a polite way of saying “never,” though ASML itself has been quick to characterise these developments as nothing but a pause [Dutch].

So, uh, what now?

As long-time industry expert Chris Mack has pointed out on his blog, Lithoguru, long-term trends have seen lithography eating an increasing percentage of total manufacturing costs every single generation. If the economics of lithography scaling no longer make sense below 14nm, the big-picture solution is to exploit improvements in a different area of the manufacturing pipeline where economics still allow for it.

Dr Mack believes that 3D transistors and the integration of TSVs (through-silicon vias) may present the only feasible way forward for microprocessor designs. There’s also talk of combining fully-depleted SOI (FD-SOI) and FinFET designs, or proceeding with the development of gate all-around transistors which would rely on nanowires – another emerging, extremely difficult area.

What’s noteworthy in all of this? The uncertainty.

For decades, semiconductor engineers have come to broad agreement about which technologies represented the best and most reliable scaling opportunities for future manufacturing. While some foundries take different paths (gate-first versus gate-last at 28nm is a good example), these could be seen as relatively minor deviations from the overarching trend. Both TSMC and GlobalFoundries implemented multiple process types of 28nm but have moved to a unified 20nm design. Both companies are moving to FinFETs, even if GF is also doing some work on FD-SOI. All of the major players were planning 450mm rollouts until quite recently.

If EUV and 450mm wafers don’t happen at 10nm, the “what happens next?” roadmap is a grab-bag of unresolved difficulties and potentially terrible economics. There are no “easy” problems left to solve, but the consequence of betting on the wrong technology could be cataclysmically expensive in terms of lost market share and enormous R&D costs. No one can afford to be wrong – but with costs skyrocketing across the board, it’s not clear if anyone can afford to be right.

Image Credit: EE Times