While Intel tinkers with 22nm wafers, and TSMC struggles to supply 40nm chips, scientists at the University of Wisconsin have developed a new lithography technique that could shrink circuits below the 10nm level.
Called molecular transfer printing (MTP), the technique uses a combination of block copolymers, which form crystal patterns that accurately reproduce etched silicon circuits. “The inks are transferred by reaction to substrates that are brought into contact with block copolymer films,” the project’s paper says, “creating chemical patterns on the substrate that mirror the domain structure present at the film surface with high fidelity and resolution.”
It’s a technique that could be used to reduce the cost of producing intricate master chips, and one of the project's leaders, Paul Nealey, told New Scientist that it can duplicate an expensive master silicon chip 20 times.
As well as this, the technique could also be used in the increasingly complicated battle to shrink silicon circuits even further. Nealey’s team performed an experiment using a standard etching technique to generate a series of parallel lines separated by 120nm. However, as the copolymer crystals formed, a pattern of lines just 30nm apart was generated.
Nealey’s team has already gone on to reproduce tiny patterns with a half-pitch on a silicon wafer, meaning that the distance between the features on the original is halved. The result is that the gaps between lines have been reduced to just 15nm.
Not only that, but Nealey is also confident that the team could easily shrink the gaps between the lines even further by using different polymers. "We will extend MTP to smaller-feature dimensions – less than 10 nanometres,” Nealey told New Scientist.
Of course, there will become a point where you can’t make silicon a circuit any smaller without challenging the laws of physics. At that point, chip makers could move over to a different material, such as graphene, in order to increase clock speeds further.