Toshiba has unveiled a new circuit design that it claims can dramatically improve the power efficiency of system-on-chips for mobile devices.
The new flip-flop circuit is based on a 40nm CMOS process, and ditches the traditional clock buffer in favour of innovative adaptive coupling circuitry based on nMOS and pMOS transistors in order to save power - resulting in a decrease in power draw of up to 77 per cent, the company claims.
To translate the move into real terms, the company claims that a Wi-Fi chip equipped with the new flip-flop circuits - and with no other changes to the remainder of the chip - draws around 24 per cent less power than one which utilises traditional clock buffered flip-flop circuitry.
Toshiba's new design doesn't just deliver impressive power savings, however: the company claims that each flip-flop configuration requires two fewer transistors than previous designs and takes up less than half the space - allowing SoC configurations to cram more technology into an ever decreasing die size.
With the SoC designs commonly found in smartphones and tablets often requiring several million flip-flop circuits, Toshiba could have stumbled onto the next big must-have technology for mobile device manufacturers - and anything that can eke a bit more life out of a mobile's battery is most certainly good news.
Toshiba has not yet confirmed when components based on the new design will be hitting the market.