JEDEC, the memory standards association, has announced the first key details regarding the next-generation DDR4 high-performance memory standard.
DDR4 - Double Data Rate, Fourth Edition - is the logical follow-up to the widely used DDR3 memory standard. Designed to improve performance while simultaneously dropping power use, DDR4 will be paired with the next generation processors from the likes of AMD, ARM, and Intel for desktop, laptop, and portable devices.
The roadmap published by JEDEC this week aims to speed migration from DDR3 to DDR4 by holding VDDQ - the supply voltage to the data storage registers - at 1.2V while maintaining headroom for a future reduction in VDD - the supply voltage for the input buffers and core logic in the memory. By keeping the IO voltage stable, JEDEC hopes to avoid any possibility that the technology will become obsolete as new power enhancements are developed.
The new DDR4 standard includes an increase in maximum theoretical performance to 3.2 gigatransfers per second per pin, from the 1.6GT/s per pin of DDR3. However, the group admits that DDR3 looks like smashing the originally set 1.6GT/s maximum, meaning that DDR4 could have its upper limit raised still further before the standard becomes set in stone.
Performance tweaks include a psuedo-open-drain inerface on the DQ bus, a geardown mode for 2,667MHz data rates and above, internally generated voltage references, and improved training modes, along with a bank group architecture that supports two or four selectable groups with separate activation, read, write, and refresh operations occurring simultaneously.
Additional features of the proposed DDR4 standard include three new data width offerings - x4, x8, and x16 - stability enhancements for the DQ bus in advance of drops in VDD voltage, improvements to the on-die termination protocol, datamasking, and new cyclic redundancy checking for the data bus even on non-ECC memory.
Putting aside the technical details, the upshot of JEDEC's announcement is, the group claims, improved reliability and performance and a lessened power draw for all DRAM-based devices.
"Numerous memory device, system, component and module producers are collaborating to finalise the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption," claimed JEDEC's DRAM Subcommittee chair Joe Macri at the announcement.
The next meeting of the committee is due in September in Chigaco, where further details of the DDR4 standard will be ironed out.