Researchers at Rice University and Hong Kong Polytechnic University have discovered a technique for creating 'walls' of graphene, which could lead to a solution for the problem of ever-shrinking chip sizes.
Published this month in the online edition of the Journal of the American Chemical Society, the researcher's detail a method of standing a ribbon of graphene - the name given to a graphite sheet just one atom thick - on its edge by supporting it with diamond or nickel.
While the contact between the diamond or nickel 'shoe' does have an impact on the nanoribbon's properties, the team claim that its electrical and magnetic properties are 'nearly all' retained following the modification.
It's a discovery which has the researchers excited about the possibility of using edge-on graphene nanoribbon 'walls' to pack trillions of field-effect transistors into a chip no larger than a single square centimetre, blowing straight past the growth predicted by Intel co-founder Gordon Moore in his eponymous 'law.'
"We met in Montreal, when nano was a new kid on the block, and had a good conversation," lead researcher Boris Yakobson recalls of Gordon Moore. "Moore liked to talk about silicon wafers in terms of real estate. Following his metaphor, an upright architecture would increase the density of circuits on a chip - like going from ranch-style houses in Texas to skyscraper condos in Hong Kong. This kind of strategy may help sustain Moore's Law for an extra decade."
While other companies have been looking at expanding into the third dimension, including Intel with its tri-gate transistor technology, few have looked as far as Yakobson. According to his calculations, walls of graphene nanoribbon could be as close together as seven-tenths of a nanometre - a significantly smaller scale than today's most common process size of 28nm.
The researchers propose two types of graphene nanowalls, each targeting a different use case: 'armchair' nanowalls can be transformed into semiconductors, while 'zigzag' nanowalls exhibit magnetic properties that could be harnessed in spintronic devices.
Sadly, the research is a long way from the implementation stage: the researchers admit that turning the theory into a commercially viable product is going to be tough, but argue that the gain in performance and power draw from a move to sub-nanometre process sizes make the project worth the effort.