Intel's announcement of test hardware based on a 14nm process size has been joined by the company's funding arm, Intel Capital, investing in nanometre scale mask and direct write lithography imaging technology outfit IMS Nanofabrication.
The funding - provided by Intel Capital, photo mask specialist Photronics and existing investor groups - will be used to push the semiconductor company's technologies below the 22nm mark and, in doing so, provide Intel with the technology it will need to commercialise its next generation semiconductor hardware.
"We are pleased to announce the funding support being provided by Intel Capital, Photronics and our existing investor groups as we work to commercialize our electron multi-beam mask exposure tool eMET for sub 22nm mask writing applications," announced Max Bayerl, IMS chief executive. "The additional resources will help IMS to demonstrate a 256 thousand e-beam mask writer column with initial exposures by the end of 2011."
The funding will be used to complete an electron multi-beam mask exposure tool proof of concept platform, designed to provide the support required for semiconductor production as process sizes dip below 22nm.
Intel's own processor architectures follow a 'tick-tock' design pattern: one year, the company launches a new architecture with enhanced performance; the year after, the company launches the same architecture on a smaller process size. By shrinking the components, more transistors can be packed into a smaller space - improving performance or reducing heat output.
As the company works towards its next-generation products, it becomes increasingly difficult to hit the 'tock' part of the design process: smaller process sizes increase complexity, while issues such as current leak can render certain design impossible.
By investing in IMS Nanofabrication, Intel is helping to ensure that it will have the tools it needs to keep its 'tick-tock' pattern going well below the 22mn mark.
"Intel Capital is pleased to support the innovation in electron multi-beam patterning being driven by IMS," crowed Keith Larson, vice president of Intel's venture capital arm. "Successful demonstration of an electron multi-beam mask writer column would be a significant step forward in addressing industry needs for higher productivity mask writing capability at finer levels of resolution."