As process nodes shrink, it’s become increasingly difficult for the major semiconductor foundries to offer compelling advantages at each new node. TSMC recently disclosed some additional information about how it intends to build 20nm chips using double patterning. The technique, while vital to constructing processors at this node, comes with some significant costs.
For nearly a decade, TSMC, GlobalFoundries, and Intel have collectively relied on argon-fluoride (ArF) lasers to etch microprocessor wafers. These lasers generate light at 193nm, deep in the ultraviolet range, and have been instrumental in driving the semiconductor industry from 90nm geometries down to 28nm. Unfortunately, 193nm light has reached its effective limit – transistor densities below 28nm are simply too small for 193nm light to etch.
How double patterning works
In single pattern lithography, a wafer is covered with a light sensitive material, known as a photoresist. Light is then streamed through a patterned photomask (a template of the chip, essentially). The light strikes the photoresist and changes the chemical properties of the material. The wafer is then bathed in a chemical solution, which washes away the areas the light touched.
This process is repeated multiple times, and the end result is (hopefully) a microprocessor.
When the silicon features become too small relative to the wavelength of light being used to etch them, however, the defect density skyrockets. Double patterning – using two photomasks, each with half of a pattern – can correct this, as shown below.
There are multiple types of double patterning and it can be used in different ways, which is why you may have heard the term before. Intel adopted it for critical areas at 45nm, when the rest of the industry was pushing immersion lithography. Then, at 32nm, TSMC and GlobalFoundries began using some double patterning, while Intel went with immersion lithography. What’s changing for TSMC at 20nm is that the company is adopting what’s called double pattern/double etch (2P2E).
(The below image shows the same cell area built with single exposure, double exposure, and double patterning. Note how the feature size and regularity improves at each step).
The big-picture takeaway from TSMC’s announcement is that while double patterning is already in use at 28nm, it’s going to be significantly more important at 20nm. Driving up the number of manufacturing steps per wafer slows down total production and increases cost, both in terms of wafers per hour and the additional tools required for the double patterning.
GlobalFoundries is also making greater use of double patterning at 20nm. Intel, meanwhile, uses the technique to a limited degree at 22nm, but has avoided the need to adopt it as widely. Chipzilla is expected to adopt double patterning at 14nm, with TSMC and GF bringing FinFET to market sometime in 2016. Long term, everyone is hoping to get extreme ultraviolet (EUV) lithography off the ground, for reasons that this next graph makes obvious.
EUV’s wavelength, at 135nm, allows for single patterning again – at least, for a little while. At 7nm, double pattern EUV may be required, but that’s far enough ahead that Intel can afford to push it back. The biggest problem with double patterning, in the end, is that it’s very much an interim solution. We were never supposed to get stuck on 193nm for as long as we have; Intel was researching 157nm lithography when it began deploying 193nm back in 2003. Problems with scaling and production ultimately killed 157nm, EUV lithography faces serious ramp issues, and none of the alternative lithography approaches have proven commercially viable.
If EUV can’t be brought online in the near future, the major semiconductor manufacturers will be talking about quad-patterning by 14-16nm – and that’s enough of a cost increase that it could seriously damage the foundry model altogether. As the number of patterns increases, the chance of a mistake in mask-switching is higher, and with the space between transistors shrinking, even a tiny mistake will cause unsustainable defects.