“Every day is a school day” and that was the case when I first came across the Tegra 4i system-on-chip which is essentially a better version of the two-year old Tegra 3 with an integrated LTE modem. I learnt back then that even ARM’s individual cores are not monolithic; indeed, the performance delta between two versions of the same cores can be very significant especially when coupled with a much high clock speed. The Tegra 4i core for example is 30 per cent faster than the one used in the Tegra 3; in addition, the 4i can run at faster clock speeds which translates into a near 2x performance gain for what is fundamentally the same product.
I reached out for ARM to get some feedback regarding the various releases for the five main processor series that it currently entertains. I ended up getting the permission to publish the product revisions for the Cortex-A5, Cortex-A7, Cortex-A8, Cortex-A9 & Cortex-A15.
I was surprised by the sheer number of updates applied to some cores. There are 14 versions of the old A8, nine versions of the A9, five for the Cortex-A7, two for the Cortex-A5 and a staggering 12 for the ARM’s current flagship processor, the Cortex-A15.
Cortex-A15
r0p0 - r0p1
The following change has been made in this release:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC0F1
Debug ID Register 0x3515F001
- Various engineering errata fixes.
r0p1 - r0p2
The following change has been made in this release:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC0F2
Debug ID Register 0x3515F002
- Various engineering errata fixes.
r0p2 - r0p3
The following change has been made in this release:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC0F3
Debug ID Register 0x3515F003
- Various engineering errata fixes.
r0p3 - r1p0
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x411FC0F0
Debug ID Register 0x3515F010
ETM ID Register 0x411CF311
Peripheral ID2 Register
0x0000001B
- Various engineering errata fixes
r1p0 - r2p0
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x412FC0F0
Debug ID Register 0x3515F020
ETM ID Register 0x411CF312
Peripheral ID2 Register
0x0000002B
- The input signals, nVIRQ and nVFIQ, are always present regardless of whether the GIC is present or not.
- L2ACTLR bit is now reserved, RAZ/WI.
- Renamed PMCCFILTR to PMXEVTYPER31 in the PMU register summary table.
- Various engineering errata fixes.
r2p0 - r2p1
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x412FC0F1
Debug ID Register 0x3515F021
- Various engineering errata fixes.
r2p1 - r2p2
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x412FC0F2
Debug ID Register 0x3515F022
- Various engineering errata fixes.
r2p2 - r3p0
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x413FC0F0
Debug ID Register 0x3515F030
ETM ID Register 0x411CF313
Peripheral ID2 Register
0x0000003B
- Added processor clock stop pins, CPUCLKOFF, configurable option.
- Added processor retention in WFI and WFE low-power state.
- Added L2ACTLR bits [26, 16:11].
- Added ACTLR2 Register.
- Various engineering errata fixes.
r3p0 - r3p1
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x413FC0F1
Debug ID Register 0x3515F031
- Various engineering errata fixes.
r3p1 - r3p2
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x413FC0F2
Debug ID Register 0x3515F032
- Various engineering errata fixes.
r3p2 - r3p3
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x413FC0F3
Debug ID Register 0x3515F033
- Various engineering errata fixes.
r3p3 - r4p0
The following changes have been made in this release:
- ID register values changed to reflect product revision status:
Main ID Register 0x414FC0F0
Debug ID Register 0x3515F040
ETM ID Register 0x411CF314
Peripheral ID2 Register
0x0000004B
- Added L2ACTLR bit[25].
- Added L1 data TLB support for 1MB page table entries.
- Various engineering errata fixes.
Cortex-A9
r0p0
First release
r0p0-r0p1
The only differences between the two revisions are:
- r0p1 includes fixes for all known engineering errata relating to r0p0
- r0p1 includes an upgrade of the micro TLB entries from 8 to 32 entries, on both the Instruction and Data side.
Neither of these changes affect the functionality described in this document.
r0p1-r1p0
Functional changes are:
- r1p0 includes fixes for all known engineering errata relating to r0p1.
- In r1p0 CPUCLKOFF and DECLKOFF enable control of Cortex-A9 processors during reset sequences.
— In a multiprocessor implementation of the design there are as many CPUCLKOFF pins as there are Cortex-A9 processors.
— DECLKOFF controls the data engine clock during reset sequences.
- r1p0 includes dynamic high level clock gating of the Cortex-A9 processor.
— MAXCLKLATENCY[2:0]bus added.
— Addition of CP15 power control register.
- Extension of the Performance Monitoring Event bus. In r1p0,
PMUEVENT is 52 bits wide:
— Addition of Cortex-A9 specific events.
— Event descriptions extended.
- Addition of PMUSECURE and PMUPRIV.
- Main TLB options for 128 entries or 64 entries.
- DEFLAGS[6:0]added.
- The power management signal BISTSCLAMP is removed.
- The scan test signal SCANTEST is removed.
- Addition of a second replacement strategy. Selection done by SCTLR.RR bit.
- Addition of PL310 cache controller optimization description.
- Change to the serializing behavior of DMB.
- ID Register values changed to reflect correct revision.
r1p0-r2p0
Functional changes are:
- Addition of optional Preload Engine hardware feature and support.
— PLE bit added to NSACR.
— Preload Engine registers added.
— Preload operations added and MCRR instruction added.
— Addition of Preload Engine events.
- Change to voltage domains.
- NEON Busy Register.
- ID Register values changed to reflect correct revision.
r2p0-r2p1
No functional changes.
r2p1-r2p2
No functional changes. Documentation updates and corrections only.
r2p2-r3p0
Addition of the REVIDR.
r3p0-r4p0
Functional changes are:
- Addition of new hardware configuration options for the TLB, BTAC, GHB & Instruction micro TLB sizes.
- Enhanced data prefetching mechanism.
r4p0-r4p1
No change
Cortex-A8
The first released version of the Cortex-A8 processor was r1p0.
r1p0-r1p1
The following changes have been made in this release:
- ID Register values changed to reflect product revision status:
Main ID Register 0x411FC081
FPSID Register 0x410330C1
- The L2EN bit of the Auxiliary Control Register is banked between Non secure and Secure states.
- SAFESHIFTRAM top-level pin added for ATPG test.
- ETM and NEON configurability support added.
r1p1-r1p2
The ID Register values changed to reflect product revision status:
Main ID Register 0x411FC082
FPSID Register 0x410330C1
r1p2-r1p3
The ID Register values changed to reflect product revision status:
Main ID Register 0x411FC083
FPSID Register 0x410330C1
r1p3-r1p7
The ID Register values changed to reflect product revision status:
Main ID Register 0x411FC087
FPSID Register 0x410330C1
r1p1-r2p0
The following changes have been made in this release:
- ID Register values changed to reflect product revision status:
Main ID Register 0x412FC080
FPSID Register 0x410330C2
- CLKSTOPREQ and CLKSTOPACK functionality added to stop and restart the processor clocks without relying on software to execute WFI instruction.
- The SAFESHIFTRAM signal is replaced with the SAFESHIFTRAMIF,
SAFESHIFTRAMLS, and SAFESHIFTRAML2signals for ATPG test.
- Intelligent Energy Management (IEM) multiple power domain support added.
- 1-way and 4-way L2 tag bank removed.
- 64KB and 2MB L2 cache sizes removed.
- ETMPWRDWNREQ and ETMPWRDWNACK are no longer required because debug and the ETM use the same power domain. ETMPWRDWNREQ must be tied to 0.
r2p0-r2p1
The ID Register values changed to reflect product revision status:
Main ID Register 0x412FC081
FPSID Register 0x410330C2
r2p1-r2p2
The ID Register values changed to reflect product revision status:
Main ID Register 0x412FC082
FPSID Register 0x410330C2
r2p1-r2p5
The ID Register values changed to reflect product revision status:
Main ID Register 0x412FC085
FPSID Register 0x410330C2
r2p2-r2p3
The ID Register values changed to reflect product revision status:
Main ID Register 0x412FC083
FPSID Register 0x410330C2
r2p2-r2p6
The ID Register values changed to reflect product revision status:
Main ID Register 0x412FC086
FPSID Register 0x410330C2
r2p2-r3p0
The following changes have been made in this release:
- ID Register values changed to reflect product revision status:
Main ID Register 0x413FC080
ID060510 Non-Confidential
FPSID Register 0x410330C3
- Improved performance for Cache Maintenance operations.
- Addition of Auxiliary Control Register bit accessible in Secure state only for controlling the performance of Cache Maintenance operations.
- Changed the PLE to perform clean-and-invalidate when DT=1 from clean.
r3p0-r3p1
The following changes have been made in this release:
- ID Register values changed to reflect product revision status:
Main ID Register 0x413FC081.
FPSID Register 0x410330C3.
- Changed the name for trigger input 0 from DBGTRIGGER to Debug entry. This trigger is a pulse asserted on debug state entry.
r3p2
ID Register values changed to reflect product revision status:
Main ID Register 0x413FC082
Cortex A7
r0p0-r0p1
Functional changes are:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC071
Debug Peripheral ID 2 0x1B
Performance Monitors Peripheral ID2 0x1B
- support for a redundant internal GIC
- various engineering errata fixes.
r0p1-r0p2
Functional changes are:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC072
Debug Peripheral ID 2 0x2B
Performance Monitors Peripheral ID2 0x2B
- various engineering errata fixes.
r0p2-r0p3
Functional changes are:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC073
Debug Peripheral ID 2 0x3B
Performance Monitors Peripheral ID2 0x3B
- enhancement of the read allocate mode operation to optimize performance
- various engineering errata fixes.
r0p3-r0p4
Functional changes are:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC074
Debug Peripheral ID 2 0x4B
Performance Monitors Peripheral ID2 0x4B
- various engineering errata fixes.
r0p4-r0p5
Functional changes are:
- ID register value changed to reflect product revision status:
Main ID Register 0x410FC075
Debug Peripheral ID 2 0x5B
Performance Monitors Peripheral ID2 0x5B
- various engineering errata fixes.
Cortex A5
r0p0 First release.
r0p0-r0p1 No functional changes.