Taiwan Semiconductor Manufacturing Company Ltd (TSMC) has announced it will be investing $25 billion in the development of 5nm chip technology.
According to the International Technology Roadmap for Semiconductors, the 5 nm node is the technology that comes after the 7 nm node.
The first demo of this technology was conducted in 2003 by NEC. In 2015, IMEC and Cadence created 5 nm test chips, which were not fully functional, but were designed to evaluate patterning of interconnect layers. The same year Intel described a lateral nanowire (or gate-all-around) FET concept for the 5-nm node.
In 2017, IBM revealed that they had created 5 nm silicon chips using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design.
Both Samsung and Intel are planning on commercialising 5 nm nodes by 2020, but TSMC has not indicated any time frame for its work.
At one point, the 5nm node was considered the end of Moore’s law. Transistors smaller than 7nm will experience quantum tunnelling through the gate oxide layer. However, there is now talk of a 3.5nm node, as well. In 2018, IMEC and Cadence had taped out 3nm test chips, and Samsung announced they plan to use Gate-All-Around technology to produce 3nm FETs in 2021.
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